Japanese patent application no. 2000-325341 filed Oct. 25, 2000 is hereby incorporated by reference in its entirety.
The present invention relates to a serial/parallel conversion circuit, a data transfer control device, and electronic equipment.
The universal serial bus (USB) standard has recently attracted attention as an interface standard for connections between personal computers and peripheral equipment (generally speaking: electronic equipment). This USB standard has the advantage of enabling the use of connectors of the same standard to connect peripheral equipment such as a mouse, keyboard, and printer, which are connected by connectors of different standards in the prior art, and of making it possible to implement plug-and-play and hot-plug features.
In comparison with the IEEE 1394 standard which is also attracting notice as a standard for the same serial bus interface, this USB standard has a problem in that the transfer speed thereof is slower.
In this case, attention is being paid to the decision to use the USB 2.0 standard which can implement a data transfer speed of 480 Mbps (in HS mode), far faster than those of the previous USB 1.1 standard, while maintaining backward compatibility with USB 1.1. The USB 2.0 transceiver macrocell interface (UTMI), which defined interface specifications for the physical-layer and logical-layer circuitry under USB 2.0, has also been determined.
An aspect of the present invention relates to a serial/parallel conversion circuit which converts serial data into parallel data, the serial/parallel conversion circuit comprising:
a data holding circuit which receives and holds serial data that is input based on a first clock;
a determination circuit which determines whether or not data held in the data holding circuit is valid, by unit of a data cell configured of a plurality of bits; and
a circuit which outputs data of a data cell that has been determined to be valid, based on a second clock having a frequency lower than a frequency of the first clock.
Another aspect of the present invention relates to a serial/parallel conversion circuit which converts serial data into parallel data, the serial/parallel conversion circuit comprising:
a data holding circuit which receives and holds serial data that is input based on a first clock;
a circuit which outputs data from the data holding circuit based on a second clock having a frequency lower than a frequency of the first clock;
a data status holding circuit which holds a status of data held in the data holding circuit; and
a write pulse generation circuit which generates first to N-th write pulse signals having pulses that go active periodically once every N clock cycles of the first clock, and a period at which a pulse of each of the first to N-th write pulse signals going active is shifted from one another by one clock cycle of the first clock,
wherein the data holding circuit holds data, based on the first to N-th write pulse signals, and
wherein the data status holding circuit holds the data status, based on the first to N-th write pulse signals.